Bing-Yue Tsui;Jui-Tse Hsiao;Ming-Han Wang;Chia-Lung Hung;Yi-Kai Hsiao;Jing-Neng Yao;Kuang-Hao Chiang;ChiaHua Ho;Hao-Chung Kuo
{"title":"A Recessed Source Contact Technology to Reduce the Specific On-Resistance of Power MOSFET on 4H-SiC","authors":"Bing-Yue Tsui;Jui-Tse Hsiao;Ming-Han Wang;Chia-Lung Hung;Yi-Kai Hsiao;Jing-Neng Yao;Kuang-Hao Chiang;ChiaHua Ho;Hao-Chung Kuo","doi":"10.1109/LED.2024.3437372","DOIUrl":null,"url":null,"abstract":"Reducing the on-resistance of SiC MOSFETs is crucial for lowering power losses and is a key aspect of MOSFET design. This letter proposes a recessed source contact (RSC) process, which utilizes the side contacts of the recessed contact structure to increase the effective contact area after narrowing the contact window width. This technology can reduce cell pitch as well as specific on-resistance without sacrificing other resistance components. In our demonstration of 1.7 kV VDMOSFETs, reducing the cell pitch from \n<inline-formula> <tex-math>$6.2~\\mu $ </tex-math></inline-formula>\nm to \n<inline-formula> <tex-math>$5.0~\\mu $ </tex-math></inline-formula>\nm by shrinking the contact width with the assistance of the RSC structure decreases the specific on-resistance by 12.6%. Conversely, without employing the RSC structure, the specific on-resistance increases by 5%. Furthermore, the RSC process allows for continuous P-well contact. Since the P\n<sup>+</sup>\n contact is embedded under the N\n<sup>+</sup>\n source, the depth and width of the P\n<sup>+</sup>\n layer are not constrained by the N\n<sup>+</sup>\n source layer.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":null,"pages":null},"PeriodicalIF":4.1000,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10621061/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Reducing the on-resistance of SiC MOSFETs is crucial for lowering power losses and is a key aspect of MOSFET design. This letter proposes a recessed source contact (RSC) process, which utilizes the side contacts of the recessed contact structure to increase the effective contact area after narrowing the contact window width. This technology can reduce cell pitch as well as specific on-resistance without sacrificing other resistance components. In our demonstration of 1.7 kV VDMOSFETs, reducing the cell pitch from
$6.2~\mu $
m to
$5.0~\mu $
m by shrinking the contact width with the assistance of the RSC structure decreases the specific on-resistance by 12.6%. Conversely, without employing the RSC structure, the specific on-resistance increases by 5%. Furthermore, the RSC process allows for continuous P-well contact. Since the P
+
contact is embedded under the N
+
source, the depth and width of the P
+
layer are not constrained by the N
+
source layer.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.