Fault-tolerant multiplier using self-healing technique

Abstract

A Field Programmable Gate Array (FPGA) is a versatile device capable of reconfiguring the logic of circuits as required. FPGAs are widely utilized in developing critical systems for space applications, defence, and aviation due to their adaptability. To facilitate the operation of these systems, a multiplier circuit is often necessary. As mission-critical systems work in a radiation environment, which affects electronic devices, the FPGA is susceptible to radiation effects that may disrupt the functionality of the configured circuit. To address this, the multiplier needs a robust fault-tolerance mechanism. Evolvable-based hardware solutions hold promise for mitigating faults, but challenges related to scalability and error recovery time persist. To address these challenges, we introduce a novel approach: a self-healing multiplier equipped with a configuration bitstream generator (CBG). This innovation effectively mitigates scalability concerns through the use of an optimized Virtual Reconfigurable Circuit (VRC) multiplier design. Additionally, the proposed solution significantly improves error recovery time through CBG integration. Our primary focus in this work is on the intrinsic approach to achieving efficient performance. In the case of the 8 × 8 multiplier, the proposed work reduces 64.59% of LUT utilization and recovers the error in 29.25 ns using an intrinsic approach. In parallel, we employ a hybrid approach to provide a comparative analysis against the intrinsic approach, demonstrating its performance. We implemented the proposed methodology on the A3PE3000 FPGA platform and conducted a comparative analysis against the proposed hybrid approach and existing methods. The results validate the superior performance and efficiency of our work using the intrinsic approach.