A High-Performance and Low HCI Degradation LDMOS Device With a Hybrid Field Plate

Abstract

In this paper, a high-performance and low-HCI (Hot carrier injection) degradation LDMOS (Lateral double diffused metal oxide semiconductor) device is introduced. It consists of an additional mini LOCOS (Local oxidation of silicon) field plate combined with a mini STI (Shallow trench isolation) field plate without an additional complex fabrication process. A series of devices have been fabricated, and the field plate corner profile is optimized. The proposed hybrid FP(Field plate) can effectively reduce the electric field peak, and the BV (Breakdown voltage) achieves as high as 78.9V while the ${R}_{{on}{,}{sp}}$ (Specific on-resistance) is as low as $69.1~{{\mathrm { m}}\Omega \cdot }{mm}^{2}$ , which is 65.8% improved compared with conventional transistors. Meanwhile, the hybrid FP device owns much better HCI (Hot carrier injection) degradation performance on ${R}_{on,sp}$ , threshold voltage ${V}_{T}$ , and gate-drain capacitance ${C}_{GD}$ . The degradation of ${R}_{{on}{,}{sp}}$ is only 8.6% under ${I}_{d}$ mode stress while it is as high as 15.8% for the conventional devices. At on-state, ${C}_{GD}$ degradation is only 9.1% while it is nearly 59.9% in the traditional device. At high voltage application regions, the device exhibits nearly 0% ${C}_{GD}$ degradation while it is as high as 43.8% in the traditional device. The results indicate the device’s robustness in both DC (Direct current) applications and RF (Radio frequency) applications.