Fast and Real-Time Thermal-Aware Floorplan Methodology for SoC

Abstract

When designing system on chip (SoC), it is crucial to ensure that the temperature stays as lowest as possible during scenario operation. For that, the placement of system blocks on the chip should be carefully planned, and simulations should be conducted repeatedly until the final temperature-optimized floorplan is determined. However, this process is time-consuming. To solve this issue, the authors propose an efficient method for calculating the temperature distribution in real-time based on thermal resistance matrix (TRM), which can help designers identify the optimal arrangement case with the lowest temperature easily. The calculated temperature distribution plots of the chip are presented, which agree with computational fluid dynamics (CFDs) results.