Interview With Janusz Rajski

IF 1.9 4区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Design & Test Pub Date : 2024-06-20 DOI:10.1109/mdat.2024.3386106

Nicola Nicolici

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引用次数: 0

Abstract

Nicola Nicolici: Good evening and I would like to welcome Janusz Rajski, a Life Fellow of IEEE, who received the Ph.D. degree in electrical engineering from Poznan textasciiacute University of Technology, Poland, in 1982. He is currently the vice president of engineering at Siemens Tessent Wilsonville, Wilsonville, OR, USA. During his tenure at Siemens, he has built a strong international research and development organization with a focus on innovative DFT technologies. His team has developed several revolutionary products widely adopted by the semiconductor industry: TestKompress, cell-aware test, and streaming scan networks. He has published 300 IEEE research papers and is a co-inventor of 130 U.S. and international patents. His papers won prestigious awards, including two best paper awards published in IEEE Transactions on CAD, one on logic synthesis and another on test compression. In 2009, Janusz received the Stephen Swerling Innovation Award from Mentor Graphics for his breakthrough innovation TestKompress and revitalizing Mentor’s DFT business to its current position as the number one test business in EDA. In 2018, he received the Siemens Inventor of the Year Lifetime Achievement Award for his extensive contributions to DFT. In 2023, he received the prestigious Bob Madge Innovation Award. Welcome, Janusz.

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专访雅努什-拉斯基

尼古拉-尼古利奇：晚上好，我想欢迎 IEEE 终身会士 Janusz Rajski，他于 1982 年获得波兰波兹南理工大学电气工程博士学位。他现任美国俄勒冈州威尔逊维尔市西门子泰森特威尔逊维尔公司工程副总裁。在西门子任职期间，他建立了一个强大的国际研发组织，专注于创新的 DFT 技术。他的团队已开发出多项被半导体行业广泛采用的革命性产品：TestKompress、单元感知测试和流扫描网络。他发表了 300 篇 IEEE 研究论文，是 130 项美国和国际专利的共同发明人。他的论文屡获殊荣，其中包括两篇发表在《IEEE CAD 杂志》上的最佳论文奖，一篇关于逻辑合成，另一篇关于测试压缩。2009 年，Janusz 荣获 Mentor Graphics 颁发的 Stephen Swerling 创新奖，以表彰他的突破性创新 TestKompress，并振兴 Mentor 的 DFT 业务，使其成为目前 EDA 领域排名第一的测试业务。2018 年，他因对 DFT 的广泛贡献而荣获西门子年度发明家终身成就奖。2023 年，他获得了享有盛誉的 Bob Madge 创新奖。欢迎您，Janusz。

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来源期刊

IEEE Design & Test COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-ENGINEERING, ELECTRICAL & ELECTRONIC

CiteScore

3.80

自引率

5.00%

发文量

期刊介绍： IEEE Design & Test offers original works describing the models, methods, and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews, and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy-efficient design, electronic design automation tools, practical technology, and standards.