Optimization of novel two-step curing method for die stack epoxy bonding to reduce voids in Ball Grid Array packages for high-density interconnect applications

IF 1.6 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Qian Qing Ng , Chou Yong Tan , Yew Hoong Wong , Boon Kar Yap , Farazila B. Yusof , Saim Saher
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Abstract

This research explores the optimization of epoxy curing parameters to minimize void formation in 3-IC-Chip-MAPBGA packages, a subset of BGA packages, crucial components in high-density interconnect applications. The study utilizes a systematic approach involving design of experiments (DOE) assisted by statistical JMP tool to manipulate curing profiles, aiming to achieve void reduction while preserving adhesion properties. Various analytical techniques, including X-ray imaging, differential scanning calorimetry (DSC), thermogravimetric analysis (TGA), die shear strength tests, and C-Sam analysis for delamination, are employed to analyze void formation, material characteristics, mechanical properties, and structural integrity. The findings demonstrate that the sample with a 2nd step curing profile, identified as sample#3, which includes a ramp time of 15 min, a 1st step curing temperature of 90 °C with a soak time of 20 min, and a 2nd step ramp time of 20 min, exhibits the most favourable outcome in void reduction. This sample shows a notably lower void presence of 3.66 % and the highest die shear strength of 126 MPa. In contrast, the control sample, serving as a reference, displays a void percentage of 7.28 %, nearly twice as high as that of sample#3, and much lower die shear strength of 80 MPa at 25 °C. Adopting the curing profile of sample#3 also leads to a substantial 18.75 % reduction in cycle time compared to the control sample. The study highlights the importance of balancing curing parameters to mitigate void formation and maintain optimal mechanical properties, offering valuable insights for improving the reliability of high-density interconnect applications.

优化用于芯片堆叠环氧树脂粘接的新型两步固化法,以减少高密度互连应用中球栅阵列封装的空隙
这项研究探索了环氧树脂固化参数的优化,以尽量减少 3-IC-Chip-MAPBGA 封装(BGA 封装的一个子集)中空隙的形成,BGA 封装是高密度互连应用中的重要组件。这项研究采用了一种系统方法,包括在统计 JMP 工具的辅助下进行实验设计 (DOE),以控制固化曲线,从而在保持粘附性能的同时减少空隙。研究采用了多种分析技术,包括 X 射线成像、差示扫描量热法 (DSC)、热重分析 (TGA)、模具剪切强度测试和分层 C-Sam 分析,以分析空隙形成、材料特性、机械性能和结构完整性。研究结果表明,采用第二步固化曲线(即 3 号样品,包括 15 分钟的斜坡时间、90 ° C 的第一步固化温度和 20 分钟的浸泡时间,以及 20 分钟的第二步斜坡时间)的样品在减少空隙方面表现最出色。该样品的空隙率明显降低,仅为 3.66%,模具剪切强度最高,达到 126 兆帕。相比之下,作为参考的对照样品的空隙率为 7.28%,几乎是 3 号样品的两倍,25 °C 时的模具剪切强度也低得多,仅为 80 兆帕。与对照样品相比,采用 3 号样品的固化曲线还可大幅减少 18.75 % 的周期时间。这项研究强调了平衡固化参数对减少空洞形成和保持最佳机械性能的重要性,为提高高密度互连应用的可靠性提供了宝贵的见解。
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来源期刊
Microelectronics Reliability
Microelectronics Reliability 工程技术-工程:电子与电气
CiteScore
3.30
自引率
12.50%
发文量
342
审稿时长
68 days
期刊介绍: Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.
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