Investigation on MOS shunt LVTSCR for ESD application

IF 1.4 4区 物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Dongyan Zhao , Yipeng Chen , Shicong Zhou , Xinyu Zhu , Yidong Yuan , Yi Hu , Tianting Zhao , Xiaojuan Li , Shurong Dong
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引用次数: 0

Abstract

Continuously scaling down ICs result in more stringent electrostatic discharge (ESD) protection design requirements. Compared with other devices, silicon-controlled rectifier (SCR) has become the first choice for its area efficiency and robustness. In order to improve the latch-up issue of SCR, various schemes have been proposed. A simple method is to extend the SCR path length, which will result in the enlarged ON resistance. Segment technology is also used to improve the holding voltage of SCR, but it will shrink the effective emitter area and lead to the serious degradation of ESD robustness. MS-LVTSCR is used to protect CMOS input ports. The circuit operating voltage is 3.3V and the gate oxide DC breakdown voltage is 19V so that considering the safety margin, the ESD window is from 3.63V to 17.1V. This work proposes a novel MOS shunt low-voltage trigger silicon-controlled rectifier (MS-LVTSCR) electrostatic discharge protection device by inserting an embedded PMOS structure. Compared with the conventional LVTSCR, the proposed MS-LVTSCR achieves 53% improvement in the holding voltage and still maintains high ESD robustness with a current level of 31.5 mA/μm without more device area consumption. In addition, both the TCAD simulation and theoretical analysis were carried out to explore the principle of current shunt effect to improve holding voltage. The extra shunt paths will weaken the conductance modulation effect of the main drift region in the main SCR path and its holding voltage can be further raised by reducing the proportion of main drift region current in the total current. We also conducted detailed studies on the mechanisms and geometry effects of this newly proposed structure via experimental validations.

有关用于 ESD 应用的 MOS 分流 LVTSCR 的研究
集成电路规模的不断缩小导致静电放电(ESD)保护设计要求更加严格。与其他器件相比,硅控整流器(SCR)因其面积效率高、坚固耐用而成为首选。为了改善可控硅的闩锁问题,人们提出了各种方案。一种简单的方法是延长可控硅路径长度,这将导致导通电阻增大。分段技术也可用于提高可控硅的保持电压,但会缩小有效发射极面积,导致 ESD 鲁棒性严重下降。MS-LVTSCR 用于保护 CMOS 输入端口。电路工作电压为 3.3V,栅极氧化物直流击穿电压为 19V,因此考虑到安全裕量,ESD 窗口为 3.63V 至 17.1V。本研究通过插入嵌入式 PMOS 结构,提出了一种新型 MOS 分流低压触发硅控整流器(MS-LVTSCR)静电放电保护器件。与传统的 LVTSCR 相比,所提出的 MS-LVTSCR 的保持电压提高了 53%,并且在不增加器件面积消耗的情况下,仍能保持较高的 ESD 鲁棒性,电流水平为 31.5 mA/μm。此外,还进行了 TCAD 仿真和理论分析,以探索提高保持电压的分流效应原理。额外的分流路径将削弱主可控硅路径中主漂移区的电导调制效应,通过降低主漂移区电流在总电流中的比例,可进一步提高其保持电压。我们还通过实验验证对这一新提出结构的机理和几何效应进行了详细研究。
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来源期刊
Solid-state Electronics
Solid-state Electronics 物理-工程:电子与电气
CiteScore
3.00
自引率
5.90%
发文量
212
审稿时长
3 months
期刊介绍: It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.
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