Fault and self-repair for high reliability in die-to-die interconnection of 2.5D/3D IC

Abstract

Bringing dies closer by die-to-die interconnection is a way that reduces latency and energy per bit transmitted, while increasing bandwidth per mm of chip. Heterogeneous integration using 2.5D/3D architectures enables disaggregation of package into various components such as input/output (IO), memory, process, and accelerator. These different functional components may be dies designed and manufactured by different companies, and multiple dies are integrated and interconnected in a package to form a multi-die system. In a multi-die package, these dies are connected using through silicon via (TSV) stacking or re-distribution layer (RDL) and TSV in the interposer according to communication protocols. However, it makes the electrical failure of its interconnection have a greater impact on reliability. Unlike interconnection of traditional integrated circuit (IC), it will bring many new challenges for fault detection and self-repair in 2.5D/3D IC. In this paper, according to unique characteristics of the die-to-die interconnection, we analyze it in top-down approach. The relevant researches on architecture, fabrication, the defect introduced, fault detection, re-routing and functional post-repair are introduced. At the end of this paper, the challenges and solutions in every stage are concluded, and the future perspectives of high reliability in die-to-die interconnection of the 2.5D/3D IC are presented.