Enhancement in electrical properties of dual-active-layer amorphous SiZnSnO/SiInZnO thin film transistors

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2024-05-09 DOI:10.1016/j.sse.2024.108952

Sandeep Kumar Maurya, Sang Yeol Lee

{"title":"Enhancement in electrical properties of dual-active-layer amorphous SiZnSnO/SiInZnO thin film transistors","authors":"Sandeep Kumar Maurya, Sang Yeol Lee","doi":"10.1016/j.sse.2024.108952","DOIUrl":null,"url":null,"abstract":"<div>Bi-layer thin film transistors (TFTs) have been fabricated with a channel structure comprising a dielectric layer, a semiconducting amorphous-Si-In-Zn-O (a-SIZO) layer, and a semiconducting amorphous-Si-Zn-Sn-O (a-SZTO) layer, aiming to improve field effect mobility and stability. These films were deposited using RF sputtering at room temperature. The TFTs with a bottom gate top contact, processed at 500 °C, exhibited high mobilities (<math><mrow><mo>></mo><mn>32</mn></mrow></math> cm<math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math> V−1 s−1) along with a current on/off ratio of approximately 10<math><msup><mrow></mrow><mrow><mn>8</mn></mrow></msup></math> and a subthreshold swing (SS) value below 0.5 V decade−1 primarily because of reduced trap density and presence of highly conducting ultrathin a-SIZO layer. Furthermore, the bi-layer TFTs demonstrated notable stability under negative and positive bias temperature stress conditions.</div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"218 ","pages":"Article 108952"},"PeriodicalIF":1.4000,"publicationDate":"2024-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110124001011","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

Bi-layer thin film transistors (TFTs) have been fabricated with a channel structure comprising a dielectric layer, a semiconducting amorphous-Si-In-Zn-O (a-SIZO) layer, and a semiconducting amorphous-Si-Zn-Sn-O (a-SZTO) layer, aiming to improve field effect mobility and stability. These films were deposited using RF sputtering at room temperature. The TFTs with a bottom gate top contact, processed at 500 °C, exhibited high mobilities ( $> 32$ cm $^{2}$ V⁻¹ s⁻¹) along with a current on/off ratio of approximately 10 $^{8}$ and a subthreshold swing (SS) value below 0.5 V decade⁻¹ primarily because of reduced trap density and presence of highly conducting ultrathin a-SIZO layer. Furthermore, the bi-layer TFTs demonstrated notable stability under negative and positive bias temperature stress conditions.

Abstract Image

查看原文本刊更多论文

增强双活性层非晶 SiZnSnO/SiInZnO 薄膜晶体管的电气性能

双层薄膜晶体管（TFT）的沟道结构包括电介质层、半导体非晶-Si-In-Zn-O（a-SIZO）层和半导体非晶-Si-Zn-Sn-O（a-SZTO）层，旨在提高场效应迁移率和稳定性。这些薄膜是在室温下通过射频溅射沉积而成的。在 500 °C 温度下处理的底栅顶部接触 TFT 显示出很高的迁移率（32 cm2 V-1 s-1），电流导通/关断比约为 108，阈下摆幅（SS）值低于 0.5 V 十年-1，这主要是由于陷阱密度降低以及存在高导电性超薄 a-SIZO 层。此外，双层 TFT 在负偏压和正偏压温度应力条件下均表现出显著的稳定性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.