{"title":"Significant Lifetime Improvement of Negative Bias Thermal Instability by Plasma Enhanced Atomic Layer Deposition SiN in Stress Memorization Technique","authors":"Cheng-Hao Liang;Zhao-Yang Li;Hao Liu;Yu-Long Jiang","doi":"10.1109/TSM.2024.3397814","DOIUrl":null,"url":null,"abstract":"In this work, the significant lifetime improvement of negative bias thermal instability (NBTI) is demonstrated by the introduction of a thin SiN layer fabricated by plasma enhanced atomic layer deposition (PEALD) in stress memorization technique (SMT). The thin SiN film is deposited before the plasma enhanced chemical vapor deposition (PECVD) of SiN layer with a high tensile stress. It is revealed that the possible H2 escape accompanied with interface de-passivation can be effectively suppressed by this thin PEALD SiN layer, which may further reduce the interface states at Si/gate dielectric interface. Hence, about 500% NBTI lifetime improvement for PMOSFETs is demonstrated without obvious performance degradation for both NMOSFETs and PMOSFETs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"405-409"},"PeriodicalIF":2.3000,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Semiconductor Manufacturing","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10521911/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this work, the significant lifetime improvement of negative bias thermal instability (NBTI) is demonstrated by the introduction of a thin SiN layer fabricated by plasma enhanced atomic layer deposition (PEALD) in stress memorization technique (SMT). The thin SiN film is deposited before the plasma enhanced chemical vapor deposition (PECVD) of SiN layer with a high tensile stress. It is revealed that the possible H2 escape accompanied with interface de-passivation can be effectively suppressed by this thin PEALD SiN layer, which may further reduce the interface states at Si/gate dielectric interface. Hence, about 500% NBTI lifetime improvement for PMOSFETs is demonstrated without obvious performance degradation for both NMOSFETs and PMOSFETs.
期刊介绍:
The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components, especially very large scale integrated circuits (VLSI). Manufacturing these products requires precision micropatterning, precise control of materials properties, ultraclean work environments, and complex interactions of chemical, physical, electrical and mechanical processes.