A low power TNU-resilient hardened latch design

Abstract

Technology scaling of integrated circuits into nanoscale feature sizes has decreased the effectiveness of existing single-node-upset and double-node-upset hardening techniques in harsh radiation environments. This paper proposes a low-power triple-node-upset resilient latch (LP-TNU) based on approximate C-elements and cross-interlocking structure. The proposed LP-TNU achieves TNU resilience based on the filtering feature of C-elements and redundant feedback structure. Extensive simulation results demonstrate the robustness of the proposed latch. The proposed LP-TNU achieves extremely low power consumption because of the clock-gating technique and fewer transistors. Compared with reference latches, the proposed latch is the most robust with the lowest power consumption and power-delay-product. In addition, compared with TNU-resilient latches such as DNUHL, LCTNURL, TNURL, HLTNURL and TNUSH, the proposed LP-TNU achieves a 62.68 % reduction on average in power consumption, 9.54 % reduction on average in delay, 20.75 % reduction on average in area overhead, 69.98 % reduction on average in the area-power-delay product. At the same time, the proposed latch is insensitive to variations of the process, supply voltage, and working temperature.