Design, simulation and analog/RF performance evaluation of a hetero-stacked source dual metal T-shaped gate tunnel-FET in thermally variable environments

Mukesh Kumar, Gautam Bhaskar, Aditya Chotalia, Chhavi Rani, Puja Ghosh, Soumak Nandi, Shashank Kumar Dubey, Kalyan Koley, Aminul Islam
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Abstract

In this work, a new Hetero-Stacked Source Dual Metal T-shaped Gate Silicon-on-Insulator (SOI) TFET (HS-DMTG-TFET) is proposed, exhibiting significantly improved DC performance, and switching performance over existing TFET topologies. A low threshold voltage of less than 200 mV in the proposed device allows for its integration in a variety of low-power applications. This device has been proposed in response to an acute need for low-power devices for bio-sensing, in situ memory, and loss-minimized switching. The proposed structure incorporates an overlapped gate pocket with a dual metal molybdenum-aluminum gate. The inclusion of a source side pocket improves the tunneling of charge carriers, which enhances the ON-state current. The Band-to-Band-Tunneling (BTBT) characteristic of TG-TFET in a direction perpendicular to the channel contributes to an elevated ON-current, attributed to a comparatively larger tunneling area. The channel exhibits a vertical U-shape, making the proposed device more scalable as compared to existing TFETs. A series of dimension and material-specific optimizations have been made and showcased in this work along with physical reasoning for the observed improvements. An ION/IOFF ratio of ~ 1014 is achieved with an ION of 1.05 × 10–3 A/μm and an IOFF of 1.35 × 10–17 A/μm. A highly reduced sub-threshold slope (lower is better) of 10.7 mV/dec is observed, indicating the good transient performance of the device. Considerable improvement in RF performance of the device has been showcased. The temperature dependence on transfer and RF characteristics has been also analyzed. The exhibited device characteristics indicate the potential of using composite material gates for low-power applications over their conventional single-metal counterparts. Reduced power consumption coupled with a compact device structure results in a minimally invasive device, suitable for low-power wearable sensors and bio-integrable circuits.

Abstract Image

热变化环境下异质叠层源双金属 T 型栅隧道场效应晶体管的设计、仿真和模拟/射频性能评估
本研究提出了一种新型异质堆叠源双金属 T 型栅极绝缘体上硅(SOI)TFET(HS-DMTG-TFET),与现有的 TFET 拓扑相比,其直流性能和开关性能均有显著提高。该器件的阈值电压低于 200 mV,可集成到各种低功耗应用中。该器件的提出是为了满足生物传感、原位存储器和损耗最小开关对低功耗器件的迫切需求。所提出的结构包含一个重叠栅极袋和一个双金属钼铝栅极。源侧口袋的加入改善了电荷载流子的隧道效应,从而增强了导通态电流。TG-TFET 在垂直于沟道方向上的带对带隧道(BTBT)特性有助于提高导通电流,这归功于相对较大的隧道面积。沟道呈垂直 U 形,因此与现有的 TFET 相比,所提出的器件更具可扩展性。本研究对器件的尺寸和特定材料进行了一系列优化,并展示了所观察到的改进的物理原理。在离子强度为 1.05 × 10-3 A/μm 和离子强度为 1.35 × 10-17 A/μm 的情况下,离子强度/离子强度比达到了 ~ 1014。阈下斜率(越低越好)大幅降低至 10.7 mV/dec,表明该器件具有良好的瞬态性能。该器件的射频性能也得到了显著改善。此外,还分析了温度对传输和射频特性的影响。所展示的器件特性表明,在低功耗应用中使用复合材料栅极比使用传统的单金属栅极更有潜力。功耗的降低与紧凑的器件结构相结合,造就了一种微创器件,适用于低功耗可穿戴传感器和生物集成电路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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