{"title":"Cryogenic Small Dimension Effects and Design-Oriented Scalable Compact Modeling of a 65-nm CMOS Technology","authors":"Alberto Gatti;Filip Tavernier","doi":"10.1109/JEDS.2024.3394167","DOIUrl":null,"url":null,"abstract":"This paper presents the cryogenic characterization and compact modeling of thin-oxide MOSFETs in a standard 65-nm Si-bulk CMOS technology. The influence of both short and narrow channel effects at extremely low temperature on key device parameters such as threshold voltage and ON current is highlighted, and the performance of this technology node for cryogenic analog circuit design is discussed. It is then demonstrated, for the widest range of gate geometries in literature, that the BSIM4 parameter editing approach can be successfully used to model small dimension effects at cryogenic temperature. In the absence of cryogenic foundry models, the robustness and simplicity of this modeling technique make it a preferred method to quickly build a design-oriented, fully scalable SPICE compact model. This restores complete freedom in device sizing for cryogenic analog circuit design.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0000,"publicationDate":"2024-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10509584","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of the Electron Devices Society","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10509584/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents the cryogenic characterization and compact modeling of thin-oxide MOSFETs in a standard 65-nm Si-bulk CMOS technology. The influence of both short and narrow channel effects at extremely low temperature on key device parameters such as threshold voltage and ON current is highlighted, and the performance of this technology node for cryogenic analog circuit design is discussed. It is then demonstrated, for the widest range of gate geometries in literature, that the BSIM4 parameter editing approach can be successfully used to model small dimension effects at cryogenic temperature. In the absence of cryogenic foundry models, the robustness and simplicity of this modeling technique make it a preferred method to quickly build a design-oriented, fully scalable SPICE compact model. This restores complete freedom in device sizing for cryogenic analog circuit design.
期刊介绍:
The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.