Universal Dielectric Breakdown Modeling Under Off-State TDDB for Ultra-Scaled Device From 130nm to 28nm Nodes and Beyond

IF 2.5 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-22 DOI:10.1109/TDMR.2024.3387271

Tidjani Garba-Seybou;Alain Bravaix;Xavier Federspiel;Joycelyn Hai;Cheikh Diouf;Florian Cacho

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引用次数: 0

Abstract

This study investigates the commonality Of TDDB under Off-state conditions across a range of CMOS nodes, from 130nm to ultra-scaled devices, i.e., 28nm FDSOI CMOS. To achieve this, Off-mode gate-oxide breakdown is analyzed under non-uniform electric field to investigate the effects of stress-induced leakage current, channel current, and lateral electric field in dielectric breakdown mechanism related to RF operations using ultra short channel devices. Oxide breakdown is characterized under DC stress with different gate-length LG as a function of drain voltage VDS and temperature. The study indicates that sub-threshold leakage current is a critical factor in determining the Off-state TDDB degradation, which is caused by a combination of band-to-band tunneling mechanism, junction current and impact ionization phenomena. The proposed Off-state TDDB compact model confirms that the leakage current is a reliable indicator of TDDB dependence precursor to hard-breakdown. Additionally, the paper discusses potential causes of the higher form factor

$\beta $

value for PFET under Off-mode stressing, which may be attributed to high impact ionization, non-conducting hot-carrier effects, defect generation kinetics and a thinner defect cell size.

查看原文本刊更多论文

针对 130 纳米至 28 纳米节点及更高节点超大规模器件的离态 TDDB 下通用介质击穿建模

本研究调查了一系列 CMOS 节点（从 130 纳米到超标量器件，即 28 纳米 FDSOI CMOS）在关态条件下 TDDB 的共性。为此，在非均匀电场条件下分析了非模式栅极氧化物击穿，以研究应力引起的泄漏电流、沟道电流和横向电场对使用超短沟道器件的射频操作相关介质击穿机制的影响。在直流应力下，不同栅极长度 LG 的氧化物击穿特性是漏极电压 VDS 和温度的函数。研究表明，阈值下漏电流是决定关态 TDDB 退化的关键因素，它是由带到带隧道机制、结电流和冲击电离现象共同造成的。所提出的离态 TDDB 紧凑模型证实，泄漏电流是 TDDB 依赖性的可靠指标，是硬击穿的前兆。此外，论文还讨论了在关态应力作用下 PFET 形状因子 $/beta $ 值更高的潜在原因，这可能归因于高冲击电离、非传导热载流子效应、缺陷产生动力学和更薄的缺陷单元尺寸。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.