ExTern: Boosting RISC-V core performance using ternary encoding

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems Pub Date : 2024-04-15 DOI:10.1016/j.micpro.2024.105058

Farhad EbrahimiAzandaryani, Dietmar Fey

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引用次数: 0

Abstract

This paper presents an effective $μ$ -architectural design method, called ExTern, to enhance the performance of a RISC-V processor experiencing computation bottlenecks. ExTern involves integrating Canonical Signed Digit (CSD) representation, a ternary number system enabling carry/borrow-free addition/subtraction in constant time $O (1)$ , into the RISC-V processor, particularly into the execution stage. Furthermore, it adopts an extended six-stage pipeline architecture to maximize employed encoding benefits, leading to more improvement in overall execution time and throughput. Despite the presence of optimized circuits, such as fast carry chain (CARRY4) modules for binary encoding on FPGA, the customized processor applying ExTern, RISC-VT, showcases remarkable improvement in computation performance. Experimental results demonstrate a 34.3% (12.2%) improvement in working frequency leading to a lower 31% (11.5%) execution time and a 32% (12%) increase in throughput compared to a State-of-the-Art open-source five(six)-stage RISC-V processor.

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ExTern：利用三元编码提升 RISC-V 内核性能

本文提出了一种有效的 μ 架构设计方法（称为 ExTern），用于提高遭遇计算瓶颈的 RISC-V 处理器的性能。ExTern 涉及将 Canonical Signed Digit (CSD) 表示法（一种三元数系统，可在 O(1) 恒定时间内实现无携带/借用加法/减法）集成到 RISC-V 处理器中，特别是集成到执行阶段。此外，它还采用了扩展的六级流水线架构，以最大限度地发挥采用编码的优势，从而进一步改善整体执行时间和吞吐量。尽管在 FPGA 上使用了用于二进制编码的快速携带链（CARRY4）模块等优化电路，但应用 ExTern 的定制处理器 RISC-VT 在计算性能方面仍有显著提高。实验结果表明，与最先进的开源五（六）级 RISC-V 处理器相比，工作频率提高了 34.3%（12.2%），执行时间缩短了 31%（11.5%），吞吐量增加了 32%（12%）。

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来源期刊

Microprocessors and Microsystems 工程技术-工程：电子与电气

CiteScore

6.90

自引率

3.80%

发文量

204

审稿时长

172 days

期刊介绍： Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.