A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Yoondeok Na;Myung-Jae Lee;Youngcheol Chae
{"title":"A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications","authors":"Yoondeok Na;Myung-Jae Lee;Youngcheol Chae","doi":"10.1109/LSSC.2024.3382594","DOIUrl":null,"url":null,"abstract":"This letter introduces a compact, high-resolution time-to-digital converter (TDC) for lidar applications. In contrast to a conventional histogram-based peak detection method, this letter proposes a mean detection method using a highly digitized phase-domain delta–sigma (PD\n<inline-formula> <tex-math>$\\Delta \\Sigma$ </tex-math></inline-formula>\n) TDC. The proposed TDC operates in an incremental \n<inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>\n manner for a compact implementation and utilizing a digital integrator as a loop filter that facilitates an extended counting, resulting in significantly improved resolution. By utilizing a dual gated-ring oscillator (GRO) structure, time-quantization noise due to a residue phase of GRO is effectively mitigated. To address the issue of single-photon avalanche diode (SPAD) signals due to their stochastic nature, a dual time window is proposed to compensate for counting error when SPAD trigger missing occurs. Fabricated in a 65-nm CMOS process, the prototype TDC occupies only an area of \n<inline-formula> <tex-math>$2000~\\mu \\text{m}~^{\\mathrm{ 2}}$ </tex-math></inline-formula>\n. It achieves a noise level of 27.6 ps for the number of cycles of 32. When the cycle is 1000, it achieves a maximum integral nonlinearity (INL) of 80 ps (+53 ps/-27 ps) with a resolution of 8.5 ps.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"127-130"},"PeriodicalIF":2.2000,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10480694/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
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Abstract

This letter introduces a compact, high-resolution time-to-digital converter (TDC) for lidar applications. In contrast to a conventional histogram-based peak detection method, this letter proposes a mean detection method using a highly digitized phase-domain delta–sigma (PD $\Delta \Sigma$ ) TDC. The proposed TDC operates in an incremental $\Delta \Sigma $ manner for a compact implementation and utilizing a digital integrator as a loop filter that facilitates an extended counting, resulting in significantly improved resolution. By utilizing a dual gated-ring oscillator (GRO) structure, time-quantization noise due to a residue phase of GRO is effectively mitigated. To address the issue of single-photon avalanche diode (SPAD) signals due to their stochastic nature, a dual time window is proposed to compensate for counting error when SPAD trigger missing occurs. Fabricated in a 65-nm CMOS process, the prototype TDC occupies only an area of $2000~\mu \text{m}~^{\mathrm{ 2}}$ . It achieves a noise level of 27.6 ps for the number of cycles of 32. When the cycle is 1000, it achieves a maximum integral nonlinearity (INL) of 80 ps (+53 ps/-27 ps) with a resolution of 8.5 ps.
用于激光雷达应用的 8.5 ps 分辨率紧凑型相位域三角积分时数字转换器
这封信介绍了一种用于激光雷达应用的紧凑型高分辨率时间数字转换器(TDC)。与传统的基于直方图的峰值检测方法不同,本文提出了一种使用高度数字化的相域三角Σ(PD $\Delta \Sigma$ )TDC 的均值检测方法。所提出的 TDC 以增量 $\Delta \Sigma $ 方式运行,实现了紧凑的结构,并利用数字积分器作为环路滤波器,便于扩展计数,从而显著提高了分辨率。通过利用双栅环振荡器(GRO)结构,GRO 的残差相位导致的时间量化噪声得到了有效缓解。为了解决单光子雪崩二极管(SPAD)信号的随机性问题,我们提出了一个双时间窗来补偿 SPAD 触发器缺失时的计数误差。原型 TDC 采用 65 纳米 CMOS 工艺制造,占地面积仅为 2000~mu \text{m}~^{\mathrm{ 2}}$。 当周期数为 32 时,它能达到 27.6 ps 的噪声水平。当周期数为 1000 时,它的最大积分非线性(INL)为 80 ps(+53 ps/-27 ps),分辨率为 8.5 ps。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Solid-State Circuits Letters
IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
3.70%
发文量
52
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