Top-gate thin-film transistors with amorphous ZnSnO channel layers prepared by pulsed plasma deposition

IF 1.4 4区 物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Yue Lan , Meng Fanxin
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Abstract

In this study, an inorganic–organic hybrid thin-film transistor (TFT) with a top-gate structure is prepared using an inorganic ZnSnO film prepared via pulse plasma deposition as the channel layer and an organic polymethyl methacrylate film prepared by the solution method as the dielectric layer. The effect of oxygen pressure during the preparation of the ZnSnO channel layer and channel-layer structure on ZnSnO TFT performance was studied. The results show that increasing the oxygen pressure during the preparation process can effectively inhibit the formation of oxygen vacancies in ZnSnO and reduce the concentration of electron carriers in ZnSnO, resulting in a reduced off current and a positive shift of the threshold voltage (Vth) in the single-channel layer ZnSnO TFT. In addition, a high-resistivity ZnSnO layer (Lt; with a lower electron-carrier concentration) is embedded between the low-resistivity ZnSnO layer (Lb; with a higher electron-carrier concentration) and the dielectric layer to form a high-/low-resistivity double-channel-layer structure (Lt/Lb). By changing the thickness combination of Lt/Lb, the resistance of the channel layer and the number of carriers modulated by gate voltage in the channel layer can be optimized, thereby adjusting the device’s on current (affecting device mobility) and key energy consumption parameters (i.e., Vth and off current) to achieve independent control. Thus, the fabricated double-channel-layer ZnSnO TFT exhibits excellent performance: high mobility (3.28 cm2/Vs), positive Vth close to 0 V (0.48 V), and on-to-off current ratio of > 105.

脉冲等离子沉积法制备的带有非晶氧化锌沟道层的顶栅薄膜晶体管
本研究以脉冲等离子体沉积法制备的无机 ZnSnO 薄膜为沟道层,以溶液法制备的有机聚甲基丙烯酸甲酯薄膜为介电层,制备了具有顶栅结构的无机-有机混合薄膜晶体管(TFT)。研究了制备 ZnSnO 沟道层和沟道层结构时氧压对 ZnSnO TFT 性能的影响。结果表明,在制备过程中增加氧压能有效抑制 ZnSnO 中氧空位的形成,降低 ZnSnO 中电子载流子的浓度,从而降低单沟道层 ZnSnO TFT 的关断电流,并使阈值电压(Vth)正向移动。此外,高电阻率 ZnSnO 层(Lt,电子载流子浓度较低)被嵌入低电阻率 ZnSnO 层(Lb,电子载流子浓度较高)和介质层之间,形成高/低电阻率双通道层结构(Lt/Lb)。通过改变 Lt/Lb 的厚度组合,可以优化沟道层的电阻和沟道层中由栅极电压调制的载流子数量,从而调整器件的导通电流(影响器件的迁移率)和关键能耗参数(即 Vth 和关断电流),实现独立控制。因此,制造出的双沟道层 ZnSnO TFT 表现出卓越的性能:高迁移率(3.28 cm2/Vs)、接近 0 V 的正 Vth(0.48 V)以及 > 105 的导通与关断电流比。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Solid-state Electronics
Solid-state Electronics 物理-工程:电子与电气
CiteScore
3.00
自引率
5.90%
发文量
212
审稿时长
3 months
期刊介绍: It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.
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