PEAR: Unbalanced Inter-Page Errors Aware Read Scheme for Latency-Efficient 3-D NAND Flash

Abstract

Although three-dimensional (3D) NAND flash memory has demonstrated impressive benefits including high capacity and storage density, data reliability is now a major worry because of long-term storage and ongoing cell wear-out. Low-density parity-check (LDPC) codes are frequently utilized in flash storage systems because of their superior error correcting capabilities to guarantee data reliability. LDPC codes can be hard-decoded or soft-decoded with significant differences depending on the raw bit error rate (RBER). By using fine-grained memory sensing operations, high RBER leads to increased decoding iterations for hard-decoding and more read levels for soft-decoding. In order to reduce the number of decoding iterations and read levels by lowering the RBER, this paper proposes an unbalanced inter-page errors aware read strategy for 3D NAND flash memory, called PEAR. A preliminary experiment is initially carried out to demonstrate that high RBER causes an increase in the number of decoding iterations and read levels. The substantial RBER fluctuation between pages is next analyzed from the viewpoint of the threshold voltage shift. Finally, PEAR properly places the read voltages between the two states with the most and second-most electrons in accordance with the phenomenon of threshold voltage drift, enabling the employment of hard-decoding with low read levels and successfully avoiding soft-decoding procedures with larger RBER. According to simulation results, PEAR can dramatically reduce RBER, decoding iterations, read levels, and read latency.