{"title":"Simulation and Optimization of IGZO-Based Neuromorphic System for Spiking Neural Networks","authors":"Junhyeong Park;Yumin Yun;Minji Kim;Soo-Yeon Lee","doi":"10.1109/JEDS.2024.3373889","DOIUrl":null,"url":null,"abstract":"In this paper, we conducted a simulation of an indium-gallium-zinc oxide (IGZO)-based neuromorphic system and proposed layer-by-layer membrane capacitor (Cmem) optimization for integrate-and-fire (I&F) neuron circuits to minimize the accuracy drop in spiking neural network (SNN). The fabricated synaptic transistor exhibited linear 32 synaptic weights with a large dynamic range \n<inline-formula> <tex-math>$(\\sim 846$ </tex-math></inline-formula>\n), and an n-type-only IGZO I&F neuron circuit was proposed and verified by HSPICE simulation. The network, consisting of three fully connected layers, was evaluated with an offline learning method employing synaptic transistor and I&F circuit models for three datasets: MNIST, Fashion-MNIST, and CIFAR-10. For offline learning, accuracy drop can occur due to information loss caused by overflow or underflow in neurons, which is largely affected by Cmem. To address this problem, we introduced a layer-by-layer \n<inline-formula> <tex-math>${\\mathrm{ C}}_{\\mathrm{ mem}}$ </tex-math></inline-formula>\n optimization method that adjusts appropriate \n<inline-formula> <tex-math>${\\mathrm{ C}}_{\\mathrm{ mem}}$ </tex-math></inline-formula>\n for each layer to minimize the information loss. As a result, high SNN accuracy was achieved for MNIST, Fashion-MNIST, and CIFAR-10 at 98.42%, 89.16%, and 48.06%, respectively. Furthermore, the optimized system showed minimal accuracy degradation under device-to-device variation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0000,"publicationDate":"2024-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10461007","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of the Electron Devices Society","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10461007/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, we conducted a simulation of an indium-gallium-zinc oxide (IGZO)-based neuromorphic system and proposed layer-by-layer membrane capacitor (Cmem) optimization for integrate-and-fire (I&F) neuron circuits to minimize the accuracy drop in spiking neural network (SNN). The fabricated synaptic transistor exhibited linear 32 synaptic weights with a large dynamic range
$(\sim 846$
), and an n-type-only IGZO I&F neuron circuit was proposed and verified by HSPICE simulation. The network, consisting of three fully connected layers, was evaluated with an offline learning method employing synaptic transistor and I&F circuit models for three datasets: MNIST, Fashion-MNIST, and CIFAR-10. For offline learning, accuracy drop can occur due to information loss caused by overflow or underflow in neurons, which is largely affected by Cmem. To address this problem, we introduced a layer-by-layer
${\mathrm{ C}}_{\mathrm{ mem}}$
optimization method that adjusts appropriate
${\mathrm{ C}}_{\mathrm{ mem}}$
for each layer to minimize the information loss. As a result, high SNN accuracy was achieved for MNIST, Fashion-MNIST, and CIFAR-10 at 98.42%, 89.16%, and 48.06%, respectively. Furthermore, the optimized system showed minimal accuracy degradation under device-to-device variation.
期刊介绍:
The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.