1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

IF 2 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of the Electron Devices Society Pub Date : 2024-03-01 DOI:10.1109/JEDS.2024.3372053

Takeya Hirose;Yuki Okamoto;Yusuke Komura;Toshiki Mizuguchi;Toshihiko Saito;Minato Ito;Kiyotaka Kimura;Hiroki Inoue;Tatsuya Onuki;Yoshinori Ando;Hiromi Sawai;Tsutomu Murakawa;Hitoshi Kunitake;Hajime Kimura;Takanori Matsuzaki;Makoto Ikeda;Shunpei Yamazaki

{"title":"1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs","authors":"Takeya Hirose;Yuki Okamoto;Yusuke Komura;Toshiki Mizuguchi;Toshihiko Saito;Minato Ito;Kiyotaka Kimura;Hiroki Inoue;Tatsuya Onuki;Yoshinori Ando;Hiromi Sawai;Tsutomu Murakawa;Hitoshi Kunitake;Hajime Kimura;Takanori Matsuzaki;Makoto Ikeda;Shunpei Yamazaki","doi":"10.1109/JEDS.2024.3372053","DOIUrl":null,"url":null,"abstract":"We present a three-dimensional (3D) DRAM prototype, which is formed using oxide semiconductor FETs (OSFETs) monolithically stacked on a Si CMOS. The OSFETs are composed of a one-layer planar FET and two-layer vertical FETs (VFETs). The 1T1C memory cells in the VFET layers and a primary sense amplifier in the planar FET layer, which are formed using heterogeneous OSFETs, provide various circuit functions in the DRAM. The operation of the 3D DRAM in a 1-Mbit memory array is demonstrated for the first time. The results show that the proposed DRAM operates with read and write times of 60 ns and 50 ns, respectively. The leakage current of the memory cell is extremely low (comparable to an \n<inline-formula> <tex-math>$2.2\\times 10^{-19}$ </tex-math></inline-formula>\n A/cell at 85°C), indicating that over 99% of the data are retained in the memory array after one hour at 85°C without refresh.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0000,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10457845","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of the Electron Devices Society","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10457845/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

We present a three-dimensional (3D) DRAM prototype, which is formed using oxide semiconductor FETs (OSFETs) monolithically stacked on a Si CMOS. The OSFETs are composed of a one-layer planar FET and two-layer vertical FETs (VFETs). The 1T1C memory cells in the VFET layers and a primary sense amplifier in the planar FET layer, which are formed using heterogeneous OSFETs, provide various circuit functions in the DRAM. The operation of the 3D DRAM in a 1-Mbit memory array is demonstrated for the first time. The results show that the proposed DRAM operates with read and write times of 60 ns and 50 ns, respectively. The leakage current of the memory cell is extremely low (comparable to an

$2.2\times 10^{-19}$

A/cell at 85°C), indicating that over 99% of the data are retained in the memory array after one hour at 85°C without refresh.

查看原文本刊更多论文

使用硅 CMOS 和异质 IGZO FET 单片叠加结构的 1-Mbit 3D DRAM

我们提出了一种三维（3D）DRAM 原型，它是利用在硅 CMOS 上单片堆叠的氧化物半导体场效应晶体管（OSFET）形成的。OSFET 由一层平面 FET 和两层垂直 FET（VFET）组成。VFET 层中的 1T1C 存储单元和平面 FET 层中的主感应放大器由异质 OSFET 组成，为 DRAM 提供各种电路功能。我们首次在 1-Mbit 存储阵列中演示了 3D DRAM 的运行。结果表明，拟议 DRAM 的读取和写入时间分别为 60 ns 和 50 ns。存储单元的漏电流极低（相当于 85°C 下 2.2/times 10^{-19}$ A/cell 的漏电流），这表明在 85°C 下不刷新的情况下，超过 99% 的数据可在一小时后保留在存储器阵列中。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Journal of the Electron Devices Society Biochemistry, Genetics and Molecular Biology-Biotechnology

CiteScore

5.20

自引率

4.30%

发文量

124

审稿时长

9 weeks

期刊介绍： The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.