Process optimization of titanium self-aligned silicide formation through evaluation of sheet resistance by design of experiment methodology

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2024-02-17 DOI:10.1016/j.sse.2024.108879

In-Chi Gau , Yao-Wen Chang , Giin-Shan Chen , Yi-Lung Cheng , Jau-Shiung Fang

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Abstract

A low-resistivity titanium silicide (TiSi₂) is crucial as a gate and source/drain material in microelectronic device fabrication, offering notable properties to enhance device performance. This study aims to experimentally determine the optimum process parameters, including arsenic doping dosage, titanium thickness, and two-step rapid thermal process (RTP) temperature, for the sheet resistance of titanium self-aligned silicide process using a design of experiment methodology. The results demonstrate that both the thickness of the titanium and the temperature of the RTP play crucial roles in determining the sheet resistance of TiSi₂. Statistical analysis reveals that increasing the titanium thickness or the temperature of the first-step RTP (RTP-1) could reduce the sheet resistance. Additionally, an optimal second-step RTP (RTP-2) temperature is critical to yield low-resistivity TiSi₂ by completely converting C49- to C54-phase. The optimum process conditions for obtaining low sheet resistance are a titanium thickness of 32–35 nm, RTP-1 temperature of 720–750 °C for 75 s, and RTP-2 temperature of 860 °C for 20 s. Moreover, surface amorphization of the polysilicon by arsenic ion implantation before the deposition of Ti/TiN films also plays a crucial role in the formation of C54-TiSi₂. The lowest sheet resistance achieved was 3.91 Ω/sq with an arsenic dosage of 1 × 10¹⁴ cm⁻². The optimum condition was adopted for forming a submicron polysilicon gate, providing a promising approach for designing the process parameters for titanium self-aligned silicide formation to achieve low resistance in nanoscale electronic devices.

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通过实验设计方法评估薄片电阻，优化钛自排列硅化物形成过程

低电阻率硅化钛（TiSi2）是微电子器件制造中至关重要的栅极和源/漏极材料，具有提高器件性能的显著特性。本研究旨在通过实验设计方法确定钛自对准硅化物工艺的最佳工艺参数，包括砷掺杂剂量、钛厚度和两步快速热工艺（RTP）温度。结果表明，钛的厚度和 RTP 的温度在决定 TiSi2 的薄层电阻方面起着至关重要的作用。统计分析表明，增加钛厚度或提高第一步 RTP（RTP-1）的温度可降低薄片电阻。此外，最佳的第二步 RTP（RTP-2）温度对于通过将 C49 相完全转化为 C54 相来获得低电阻率 TiSi2 至关重要。获得低薄片电阻的最佳工艺条件是：钛厚度为 32-35 nm，RTP-1 温度为 720-750 ℃，持续 75 秒，RTP-2 温度为 860 ℃，持续 20 秒。此外，在 Ti/TiN 薄膜沉积之前，通过砷离子注入对多晶硅进行表面非晶化，也对 C54-TiSi2 的形成起到了关键作用。在砷用量为 1 × 1014 cm-2 时，获得的最低薄层电阻为 3.91 Ω/sq。该方法采用了形成亚微米多晶硅栅极的最佳条件，为设计钛自排列硅化物形成的工艺参数以实现纳米级电子器件的低电阻提供了一种可行的方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.