Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

IF 1.4 4区 物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Michelly de Souza , Antonio Cerdeira , Magali Estrada , Mikaël Cassé , Sylvain Barraud , Maud Vinet , Olivier Faynot , Marcelo A. Pavanello
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Abstract

This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For a fixed gate voltage, the channel length reduction increases the GIDL current except in the presence of short-channel length. Three-dimensional TCAD simulations were performed, and the band-to-band generation was extracted for devices with different channel lengths, widths, and temperatures. The temperature rise increases valence and conduction energy levels, being more pronounced in the first, which causes the reduction of the lateral distance between the two levels, finally favoring the transversal band-to-band tunneling.

全面评估在高温下工作的 SOI 叠层纳米线 nMOSFET 中的栅极诱导漏极泄漏
本文对工作温度介于 300 K 和 580 K 之间的两级堆叠纳米线 SOI nMOSFET 的栅极诱导漏电流(GIDL)进行了全面的实验分析。测量了不同沟道长度和鳍片宽度的器件。结果表明,温度升高会增大堆叠纳米线晶体管的 GIDL 电流,而且 GIDL 电流与纳米线宽度有关。在栅极电压固定的情况下,除短沟道长度外,沟道长度的减少会增加 GIDL 电流。我们进行了三维 TCAD 仿真,并提取了具有不同沟道长度、宽度和温度的器件的带到带发电量。温度升高会增加价能级和传导能级,前者更为明显,从而导致两个能级之间的横向距离减小,最终有利于横向带对带隧道。
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来源期刊
Solid-state Electronics
Solid-state Electronics 物理-工程:电子与电气
CiteScore
3.00
自引率
5.90%
发文量
212
审稿时长
3 months
期刊介绍: It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.
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