Hot-carrier induced degradation of Ge/STI interfaces in Ge-on-Si junction devices

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2024-02-02 DOI:10.1016/j.sse.2024.108867

Solomon Musibau , Jacopo Franco , Artemisia Tsiara , Ingrid De Wolf , Kristof Croes

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Abstract

The degradation of Ge junctions epitaxially grown within shallow trench isolation (STI) on Si is investigated for geometries with different Area-to-Perimeter (A/P) ratios under constant-voltage stress. We show that the reverse-bias relative current shift ( $Δ I (t) / I_{0}$ ) exhibits a two component behaviour ascribed to the interplay between charge trapping in (pre-existing) traps and generation of new defects mostly along the perimeter of the junctions (Ge/STI interfaces), which affect the trap assisted tunnelling (TAT) leakage current. A semi-empirical model of the degradation kinetics is proposed, allowing to decouple the role of the two individual degradation mechanisms. The insights and the methodology presented are expected to be of relevance for Ge-on-Si active components for Silicon Photonics applications.

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硅结 Ge 器件中 Ge/STI 接口的热载流子诱导降解

我们研究了在恒压应力作用下，不同面积与周长（A/P）比的硅上浅沟槽隔离（STI）外延生长的 Ge 结的退化情况。我们发现，反向偏置相对电流偏移（ΔI(t)/I0）表现出两部分行为，这归因于电荷在（先前存在的）陷阱中的捕获和新缺陷的产生（主要是沿着结的周边（Ge/STI 接口））之间的相互作用，后者会影响陷阱辅助隧穿（TAT）泄漏电流。我们提出了降解动力学的半经验模型，从而将两种降解机制的作用分离开来。所提出的见解和方法有望用于硅光子学应用中的硅基有源元件。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.