A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2024-01-11 DOI:10.1109/LSSC.2024.3352736

Hóngyè Huáng;Bangan Liu;Zezheng Liu;Dingxin Xu;Yuncheng Zhang;Waleed Madany;Junjun Qiu;Zheng Sun;Ashbir Aviat Fadila;Jian Pang;Zheng Li;Dongwon You;Atsushi Shirane;Kenichi Okada

{"title":"A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range","authors":"Hóngyè Huáng;Bangan Liu;Zezheng Liu;Dingxin Xu;Yuncheng Zhang;Waleed Madany;Junjun Qiu;Zheng Sun;Ashbir Aviat Fadila;Jian Pang;Zheng Li;Dongwon You;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2024.3352736","DOIUrl":null,"url":null,"abstract":"This letter describes a fully synthesizable fractional-\n<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\n multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding predistortion look-up table (LUT)’s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC’s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of −242.3 and −218.6 dB in integer-\n<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\n and fractional-\n<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\n operation modes at RF frequencies 1.04 and 1.0465 GHz. The core area is 0.0892 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"54-57"},"PeriodicalIF":2.2000,"publicationDate":"2024-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10391060","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10391060/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

This letter describes a fully synthesizable fractional-

$N$

multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding predistortion look-up table (LUT)’s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC’s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of −242.3 and −218.6 dB in integer-

$N$

and fractional-

$N$

operation modes at RF frequencies 1.04 and 1.0465 GHz. The core area is 0.0892 mm2.

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基于高能效环形振荡器的大调谐范围 DTC 的完全可合成分数 N MDLL

这封信描述了一种完全可合成的分数-N$复用延迟锁定环（MDLL），它具有基于环振荡器的数字-时间转换器（RO-DTC）。拟议的 RO-DTC 只需相对较少的延迟单元，就能产生较大范围的时间延迟。由于其结构是周期性的，因此相应的预失真查找表（LUT）的大小也可以减小。拟议的 MDLL 采用 65 纳米 CMOS 工艺实现。测量结果表明，RO-DTC 按工作频率和调谐范围归一化后的功率是其他先进产品中最低的。在射频频率为 1.04 和 1.0465 GHz 时，拟议 MDLL 在整数-N$和分数-N$工作模式下的 FoM 分别为 -242.3 和 -218.6 dB。核心面积为 0.0892 mm2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量