A novel hybrid fast Fourier transform processor in 5G+ and bio medical applications

IF 1.9 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
R. Priyadharsini, S. Sasipriya
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引用次数: 0

Abstract

To address the growing demand for real-time and high-performance signal processing, Field-Programmable Gate Array (FPGA) technology provides an influential platform for implementing Fast Fourier Transform (FFT) algorithms. The existing topologies of FFT processors encounters challenges related to high power consumption, limiting their viability for energy-efficient applications. In this research work, a hybrid radix encoder with two-stage operand trimming logarithmic appropriate multiplier and optimized truncated Kogge-stone adder based 2048-point, 4096-point FFT processor for FPGA implementation is designed by focusing on high throughput with minimal consumption of power. This processor is engineered to handle FFTs ranging from 16 to 4096 points catering to both biomedical applications and upcoming 5G technology. The proposed/introduced framework attains a high throughput (78.036 Gbps), and maximum signal to noise ratio (30 dB), low power consumption (26.49 mW), minimum delay (0.12 ns), minimum area (547 μm2), bit error rate (0.1) and minimum execution time (0.223 ms) than the traditional approaches.

5G+ 和生物医学应用中的新型混合快速傅立叶变换处理器
为满足对实时和高性能信号处理日益增长的需求,现场可编程门阵列(FPGA)技术为实现快速傅立叶变换(FFT)算法提供了一个极具影响力的平台。现有的 FFT 处理器拓扑结构面临着高功耗的挑战,限制了其在高能效应用中的可行性。在这项研究工作中,设计了一种混合弧度编码器,带有两级操作数修剪对数适当乘法器和优化的截断 kogge-stone 加法器,基于 2048 点、4096 点 FFT 处理器,用于 FPGA 实现,重点关注高吞吐量和最小功耗。该处理器可处理 16 至 4096 点的 FFT,满足生物医学应用和即将到来的 5G 技术的需要。与传统方法相比,拟议/引入的框架实现了高吞吐量(78.036 Gbps)、最大信噪比(30dB)、低功耗(26.49 mW)、最小延迟(0.12 ns)、最小面积(547 μm2)、误码率(0.1)和最短执行时间(0.223 ms)。
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来源期刊
Microprocessors and Microsystems
Microprocessors and Microsystems 工程技术-工程:电子与电气
CiteScore
6.90
自引率
3.80%
发文量
204
审稿时长
172 days
期刊介绍: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.
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