Parametrized low-complexity hardware architecture of an H.264-based video encoder for FPGAs

IF 1.9 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Microprocessors and Microsystems Pub Date : 2024-01-13 DOI:10.1016/j.micpro.2024.105017

Azam Tayyebi , Darrin Hanna , Bryant Jones

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引用次数: 0

Abstract

This paper presents a scalable, efficient, and real-time intra H.264 video encoder architecture designed for FPGAs. The system achieves up to 2.3 Gbit/s throughput using parallel and pipelined architecture described in VHDL. The architecture prioritizes hardware efficiency, with all modules optimized for minimal resource usage. It proposes a parametrized encoding system and a flexible design with varying size and power requirements. As a baseline, the encoder utilizes 18K logic gates with no compression while the experimental compression ratios up to 2.7 require around 51.5K logic gates. The encoder operates efficiently at frequencies between 115 and 183 MHz. This study is important as it offers a high-speed, hardware-optimized video encoding on FPGA devices. It satisfies the demands of multi-channel encoding applications. Current encoders consume significant hardware resources, constraining the possibility of deploying multiple encoders on a single FPGA device for simultaneous encoding of multiple video channels.

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基于 H.264 的 FPGA 视频编码器的参数化低复杂度硬件架构

本文介绍了一种专为 FPGA 设计的可扩展、高效和实时的 H.264 内部视频编码器架构。该系统采用 VHDL 描述的并行和流水线架构，吞吐量高达 2.3 Gbit/s。该架构优先考虑硬件效率，对所有模块进行了优化，以实现最低的资源使用率。它提出了一个参数化编码系统和一个灵活的设计，可满足不同的尺寸和功耗要求。作为基线，编码器在不压缩的情况下使用 18K 逻辑门，而实验压缩率高达 2.7 时则需要约 51.5K 逻辑门。编码器可在 115 至 183 MHz 频率范围内高效运行。这项研究非常重要，因为它在 FPGA 设备上提供了高速、硬件优化的视频编码。它能满足多通道编码应用的需求。目前的编码器消耗大量硬件资源，限制了在单个 FPGA 器件上部署多个编码器同时对多个视频通道进行编码的可能性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microprocessors and Microsystems 工程技术-工程：电子与电气

CiteScore

6.90

自引率

3.80%

发文量

204

审稿时长

172 days

期刊介绍： Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.