{"title":"Performance potential of transistors based on tellurium nanowire arrays: A quantum transport study","authors":"Ning Yang, Jing Guo","doi":"10.1016/j.sse.2024.108859","DOIUrl":null,"url":null,"abstract":"<div><p>Low-dimensional nanomaterials provide promising material platforms for aggressively scaled transistor technologies. We assess the performance potential of transistors based on an array of Tellurium nanowires (TNWs), by parameterizing a machine-learning (ML) tight-binding model with quantum transport device simulations. It has been shown that a transistor based on a parallel array of carbon nanotubes (CNTs) can have excellent on-state performance, but the small bandgap limits the transistor scalability and off-state performance. Our results indicate that compared to the CNT array FETs, the TNW array FETs have significantly suppressed ambipolar transport and improved subthreshold characteristics. The TNW array FET has the potential to achieve a near-ideal subthreshold swing (SS) close to 60 mV/dec, a very large on–off ratio (>10<sup>9</sup>), and low source-drain leakage current at a 10 nm-scale channel length, due to its excellent gate electrostatics with a gate-all-around (GAA) structure, larger band gap and reduced quantum–mechanical tunneling. The TNW array FET also shows excellent scalability with a SS below 100 mV/dec when the channel length is further scaled down to 5 nm. Its larger bandgap and heavier effective mass significantly reduce quantum tunneling. This mechanism contributes to improved subthreshold and lower leakage but also highlights the need to develop low Schottky barrier contacts for TNWs.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4000,"publicationDate":"2024-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S003811012400008X","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Low-dimensional nanomaterials provide promising material platforms for aggressively scaled transistor technologies. We assess the performance potential of transistors based on an array of Tellurium nanowires (TNWs), by parameterizing a machine-learning (ML) tight-binding model with quantum transport device simulations. It has been shown that a transistor based on a parallel array of carbon nanotubes (CNTs) can have excellent on-state performance, but the small bandgap limits the transistor scalability and off-state performance. Our results indicate that compared to the CNT array FETs, the TNW array FETs have significantly suppressed ambipolar transport and improved subthreshold characteristics. The TNW array FET has the potential to achieve a near-ideal subthreshold swing (SS) close to 60 mV/dec, a very large on–off ratio (>109), and low source-drain leakage current at a 10 nm-scale channel length, due to its excellent gate electrostatics with a gate-all-around (GAA) structure, larger band gap and reduced quantum–mechanical tunneling. The TNW array FET also shows excellent scalability with a SS below 100 mV/dec when the channel length is further scaled down to 5 nm. Its larger bandgap and heavier effective mass significantly reduce quantum tunneling. This mechanism contributes to improved subthreshold and lower leakage but also highlights the need to develop low Schottky barrier contacts for TNWs.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.