Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing

Abstract

Cryogenic operation of CMOS transistors (i.e., cryo-CMOS) effectively brings an ultrasteep subthreshold slope (SS) and ultralow leakage, enabling high energy efficiency with appropriate tuning of threshold voltage and supply voltage. On the other hand, cryo-CMOS suffers from elevated sensitivity to process and voltage variations. To facilitate early-stage design exploration, we develop predictive BSIM-CMG model cards, which are calibrated with 14 nm TCAD simulation and our experimental FinFET data from 300 to 77 K. These models are scalable with temperatures from 300 K down to 77 K, device engineering and variations. Based on them, we benchmark various circuit examples to illustrate the tremendous potential of cryo-CMOS for energy-efficient computing, in the presence of process variations. For logic circuits, such as a canonical critical path, more than $15\times $ reduction in total energy consumption is demonstrated at 77 K for the iso–Delay condition, compared to the operation at the room temperature (RT). The presence of variations only has a marginal impact on energy efficiency, after threshold voltage and supply voltage are adaptively increased. For static noise margin (SNM), it is consistently improved at 77 K. However, the impact of variations on SNM is much more pronounced than that on logic circuits.