Damage Assessment Structure of Test-Pad Post-Processing on CMOS LSIs

Abstract

We assessed potential degradation of MOSFET characteristics induced by post-processing of extra bond pads. The pads are used as stable electrical connections in repairing and test. The test structure consists of $\pmb{16\times 16}$ arrayed PMOSFETs designed with 0.6 $\pmb{\mu}\mathbf{m}$ CMOS technology. An aluminum pad is deposited on the arrayed structure using a silicon shadow mask, and wire bonding is performed subsequently. The characteristics of $I_{\mathrm{d}}-V_{\mathrm{g}}$ were compared before and after the post-process. The result indicates that the post-processing does not affect the characteristics of MOSFETs, and therefore it can be used to place post-processed bond pads over an LSI chip.