A low-cost MCM implementation for 100-Hz TV up-conversion

Abstract

A system-on-chip covering all 100 Hz TV digital signal processing functions has been implemented as a MCM in a P-MQFP-64 package. The design, architecture, test concept and special arrangement of two chips assembled together are presented. The yield improvement of the larger memory chip achieved by redundancy optimization has led to a profitable product with higher yield and lower costs than previous multi-package solutions. This development was based on state-of-the-art technology, using materials that were as standard as possible and included DFT (design for testability) right from the outset, i.e. sufficient flexibility to test every block of a multichip module. The time-to-market requirements were effectively satisfied by implementing the system as a MCM. The rough estimate made here shows that when it comes to implementing future high-performance on-chip systems with advanced logic and memory integration, the obvious choice is an emergent embedded DRAM technology.