An Infrastructure IP for Repairing Multiple RAMs in SOCs

2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI:10.1109/VDAT.2006.258150

Chao-Da Huang, Tsu-Wei Tseng, Jin-Fu Li

引用次数: 12

Abstract

Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories-based on TSMC 0.18mum standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%

查看原文本刊更多论文

用于修复soc中多个ram的基础架构IP

现代复杂的片上系统(soc)需要基础设施ip来测试、诊断和修复嵌入式存储器。本文提出了一种用于修复soc中多个ram的基础架构IP (IIP)。所提出的IIP可以对多个记忆体进行并行测试，每次对一个记忆体进行串行诊断或修复。特别地，所提出的IIP可以执行各种冗余分析算法。我们实现了基于台积电0.18 μ m标准电池技术的四存储器IIP。实验结果表明，IIP的面积开销仅为4.6%左右

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2006 International Symposium on VLSI Design, Automation and Test

自引率

0.00%

发文量