Process development for 3D integration: Conductive wafer bonding for high density inter-chip interconnection

Abstract

This paper discusses the application of conductive wafer bonding, especially wafer level hybrid Cu-Cu bonding, for realizing high density inter-chip interconnection. 3D integration process using conductive wafer bonding and the test vehicle for bonding process evaluation are described. Different pre-bonding surface treatment methods and bonding procedures are studied and compared for yield and throughput optimization.