3D solid modeling of IC structures using simulated surface topography

Abstract

The importance of 3D effects in semiconductor processes and devices is growing as structures are scaled into the deep submicron regime. In order to perform 3D analysis, however, designers need to accurately specify the structure to be simulated. A virtual integrated process modeling tool, based on a set of techniques which enable the construction of 3D device structures, is presented with emphasis on a new technique to build 3D LOCOS geometries. Examples illustrate how this technique is used to construct both a test structure as well as an actual memory cell design.