VHSIC phase 2 test requirements for the depot

Abstract

The recently released Phase 2 very high speed integrated circuits (VHSIC) standards show that VHSIC will operate up to 100 MHz. The author examines the ATE (automatic test equipment) test capability that will be required for these high-performance digital circuits and whether new ATE capability will be required or whether present technology will be sufficient. His analysis shows that using the VHSIC Phase 2 interface buses (PI bus, TM-bus, and ETM-bus) and maximizing the use of system/module/IC built-in-test, a 25-MHz tester can satisfy depot test requirements. In addition, bus interface circuits designed to emulate the internal/external event-driven VHSIC bus protocols at operational speeds facilitate this concept.<>