A BIST approach for counterfeit circuit detection based on NBTI degradation

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) Pub Date : 2015-10-01 DOI:10.1109/DFT.2015.7315148

Puneet Ramesh Savanur, Phaninder Alladi, S. Tragoudas

引用次数: 7

Abstract

This paper presents a simple BIST enhancement to detect counterfeit circuits which experience aging delays. The approach is based on the NBTI aging factor. HSPICE simulations on 45nm and 65nm technologies using a predictive NBTI degradation model are presented. The results indicate that counterfeit circuits undergone minimal stress are detected consistently in the presence of process variations.

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基于NBTI退化的BIST伪电路检测方法

本文提出了一种简单的BIST增强方法来检测具有老化延迟的假冒电路。该方法基于NBTI老化因子。采用预测NBTI降解模型对45nm和65nm工艺进行了HSPICE仿真。结果表明，在存在工艺变化的情况下，经过最小应力的伪造电路始终被检测到。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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