Power islands: a high-level technique for counteracting leakage in deep sub-micron

Abstract

With the migration to deep sub-micron (DSM) process technologies, the static power (leakage) has become the major contributor to the design's overall power consumption. In this work, we show experiments that illustrate the significant increase in the ratio of the leakage to the total power as the DSM process nodes shrink. We also present a high-level design/synthesis method, called power islands that minimize the leakage in the circuit by partitioning it into islands. Each island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and hence can be completely powered down when all the logic contained within it is idling. The partitioning is done in such a way that the components with maximally overlapping lifetimes are placed on the same island. A main benefit of power islands is the elimination of leakage in inactive components during the power down cycles of the islands, and hence a decrease in circuit's power consumption. The effectiveness of the proposed technique is demonstrated through several examples implemented with 4 different feature sizes: 180 nm, 130 nm, 100 nm and 70 nm. These experiments showed improvements in leakage ranging from 41% to 80% at 70 nm due to power islands