The soot deposited integrated circuit substrate of 6 inches diameter for high voltage ICs, improved in durability against the pressure cooker test

Abstract

We have developed a dielectrically isolated substrate for a high voltage transistor applying the SODIC process. It was shown that the SODIC substrate had the advantage of low warpage and no void. However, the durability of the glass layer became a problem with cracking of the glass layer after pressure cooker test (PCT). It was found that the generation of cracks depended on the Si/B ratio and that the glass layer had the large distribution of the Si/B ratio. We have succeeded in improving the durability of SODIC substrate against PCT by making the concentration of the soot layer uniform and making the high voltage transistors on a 6-inch substrate, which showed a breakdown voltage of over 350 V.