Design of a Capacitance Measurement Circuit with Input Parasitic Capacitance Elimination

Abstract

This paper proposes a capacitance sensing circuit which converts the change of input capacitance into digital code as output signal. The whole CDC circuit is designed using SMIC 0.18\ \mu\mathrm{m}$ CMOS process technology in cadence. It contains an AFE circuit and an advanced single-slop ADC circuit. The CDC circuit which has a high dynamic range can measure the capacitor ranging from 1fF to 1pF, even with the large input parasitic capacitance. The AFE module is improved base on traditional C-V by adding subtracting and level shifting circuit to eliminate the influence of parasitic capacitor in the circuit. Simulation results show that the sensitivity of the AFE circuit is 0.95 fF/mV and the sensitivity of the CDC circuit is 1 fF/digital. Conversion time for each measurement is $65\ \mu\mathrm{s}$ and the current consumption of the circuit is 1.1 mA.