Thermal impact of solder voids in the electronic packaging of power devices

Abstract

The subject of this paper is the thermal impact of solder voids in the electronic packaging of semiconductor power devices. First, the pros and cons of some conventional methods used in thermal analysis are assessed, with emphasis on the accuracy of the commonly-used 45/spl deg/ model in calculating thermal resistance. Finite element thermal analysis is then applied to the case of different solder voids, which are classified and modeled numerically. The thermal resistance for each case is calculated and compared. It is found that different kinds of solder voids have a quite different impact upon the overall package thermal impedance. Large, coalesced voids have a more significant effect than small, distributed voids. The influence of solder voids on the example of a semiconductor laser chip is also analyzed. It is found that the long strip-type heat generating areas/volumes associated with semiconductor laser chips result in a strong sensitivity to the orientation of solder voids underneath. Finally, solder joint inspection criteria outlined in MIL-STD-883D method 2030 are discussed. Some possible modifications are proposed for the inspection of solder joints in semiconductor laser chip bonding.