A fault model for switch-level simulation of gate-to-drain shorts

P. Dahlgren, P. Lidén
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引用次数: 7

Abstract

An efficient algorithm for analyzing a subset of transistor-level bridging faults is proposed. The complex analogue behavior of gate-to-drain shorts is handled using a network primitive into which the fault injected transistor is mapped. The resistances of the surrounding subnetworks obtained from a linear switch-level model are used together with a simple iteration scheme to predict the voltage at the shortened nodes. Fault simulation experiments were conducted and the algorithm shows good agreement with electrical-level analysis.
闸-漏短路开关级仿真的故障模型
提出了一种分析晶体管级桥接故障子集的有效算法。栅极-漏极短路的复杂模拟行为使用网络原语处理,其中故障注入晶体管被映射到网络原语中。利用线性开关级模型得到的周围子网的电阻,结合简单的迭代方案来预测缩短节点处的电压。仿真实验表明,该算法与电级分析结果吻合较好。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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