{"title":"A fault model for switch-level simulation of gate-to-drain shorts","authors":"P. Dahlgren, P. Lidén","doi":"10.1109/VTEST.1996.510887","DOIUrl":null,"url":null,"abstract":"An efficient algorithm for analyzing a subset of transistor-level bridging faults is proposed. The complex analogue behavior of gate-to-drain shorts is handled using a network primitive into which the fault injected transistor is mapped. The resistances of the surrounding subnetworks obtained from a linear switch-level model are used together with a simple iteration scheme to predict the voltage at the shortened nodes. Fault simulation experiments were conducted and the algorithm shows good agreement with electrical-level analysis.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 14th VLSI Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1996.510887","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
An efficient algorithm for analyzing a subset of transistor-level bridging faults is proposed. The complex analogue behavior of gate-to-drain shorts is handled using a network primitive into which the fault injected transistor is mapped. The resistances of the surrounding subnetworks obtained from a linear switch-level model are used together with a simple iteration scheme to predict the voltage at the shortened nodes. Fault simulation experiments were conducted and the algorithm shows good agreement with electrical-level analysis.