Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts

Abstract

This paper provides an overview of metallic source/drain (MSD) Schottky-barrier (SB) MOSFET technology. This technology offers several benefits for scaling CMOS, i.e., extremely low S/D series resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of this technology needs to overcome new obstacles such as Schottky barrier height (SBH) engineering and careful control of SALICIDE process. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. Recently, we have invested a lot of efforts on Pt- and Ni-silicide MSD SB-MOSFETs and achieved some promising results. The present work, together with the work of other groups in this field, places silicide MSD SB-MOSFETs as a competitive candidate for future generations of CMOS technology.