Yield enhancement methodology for CMOS standard cells

Abstract

In order to maximize the yield of random logic in today's advanced deep sub-micron CMOS technologies we have developed a complete yield enhancement methodology for CMOS standard cells. This methodology based on a test vehicle approach covers design, industrial test, data collection and volume analysis, design debug, failure location and analysis. It has proven to be successful on three consecutive technology nodes down to 65nm. This paper explains the methodology and demonstrate the results and benefits of this work through illustrated examples