A numerical model for simulating MOSFET gate current degradation by considering the interface state generation

1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095) Pub Date : 1900-01-01 DOI:10.1109/SISPAD.1996.865301

C. Yih, S.S. Chung, C. Hsu

引用次数: 4

Abstract

In this paper, a new gate current degradation model for n-MOSFET's by considering the interface state generation is proposed. This interface state has been characterized using a new approach and incorporated into a 2D device simulation for predicting the device gate current characteristics due to a hot carrier stress induced effect. Good agreement of the gate current has been achieved as compared with the measurement data for both fresh and stressed devices. This model is not only useful for predicting the gate current degradation, but also as a superior monitor to substrate current for submicron device reliability issues, in particular EPROM or flash EPROM devices.

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一种考虑界面态产生的MOSFET栅极电流退化的数值模型

本文提出了一种考虑界面态产生的n-MOSFET栅极电流衰减模型。使用一种新的方法表征了这种界面状态，并将其纳入二维器件模拟中，以预测由于热载子应力诱导效应而导致的器件栅极电流特性。与新鲜和受压装置的测量数据相比，门电流得到了很好的一致性。该模型不仅可用于预测栅极电流退化，而且还可作为亚微米器件可靠性问题，特别是EPROM或闪存EPROM器件的衬底电流的优越监视器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)

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