Numerical simulations of surface states effects on GaAs power MESFETs

1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095) Pub Date : 1996-09-02 DOI:10.1109/SISPAD.1996.865302

P. Francis, Y. Ohno, M. Nogome, Y. Takahashi

引用次数: 1

Abstract

Summary form only given. The effects of surface states on the gate offset regions of GaAs power MESFETs are analyzed using a two-dimensional device simulator with a Shockley-Read-Hall statistics model for the surface states. Assuming electron trap type surface states and hole trap type surface states, it is found that the trap properties cause a large difference in DC performance and pulse operation of the FETs.

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表面态对GaAs功率mesfet影响的数值模拟

只提供摘要形式。利用二维器件模拟器和表面态统计模型，分析了表面态对GaAs功率mesfet栅极偏置区的影响。在假设电子陷阱型表面态和空穴陷阱型表面态的情况下，发现陷阱的性质会导致fet的直流性能和脉冲工作有很大的差异。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)

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