Wafer-level Re-Packaging of Commercial Components for Miniaturization and Embedding

Abstract

Integrated circuits packaged as commercial of the shelf components (COTS) are usually designed for robust handling in standard SMT-processes. They are often too bulky to be embedded in a multilayer PCB and pose limitations for higher component densities on boards. On the other hand, bare dies which could be applied as FlipChip or Chip-on-Board are often not available for customers with medium or low volume products. The suggested technology provides an option to address this issue by a re-packaging process of wire bonded or Au-FlipChip bonded dies in wafer format. Standard packages are mounted and overmolded on a temporary carrier wafer in a matrix like structure. The wafer is thinned down to reduce package height and to get access to wire bonds or stud bumps. Thin film deposition of adhesion layer and plating base followed by polymer photoresist lithography and electroplating is used to create a redistribution pattern which - depending on the area available – can be fan-in or fan-out type. After stripping of the photoresist and etching of the plating base and adhesion layer solder mask and solder bumps may be applied to achieve a SMT-compatible component. Finally, the individual packages are separated by wafer sawing. For packages intended to be used for PCB embedding solder mask and bumping processes are skipped. The entire process is demonstrated based on a Small Outline package with the dimensions 5 mm × 6.3 mm × 1.75 mm (length, width, height). The re-packaged component has a lateral size of 3.2 × 3.2 mm2 and a height of 0.35 mm.