A 16bit 1MS/s High-Bit Sampling SAR ADC with Improved Binary-Weighted Capacitive Array

Abstract

This paper presents a 16-bit 1MS/s successive approximation register (SAR) analog-to-digital converters (ADC) for precision measurement in 180nm technology. High-bit sampling makes the bridge capacitor become unit capacitance, which solves the problem of fractional capacitor mismatch. In addition, thermometer-coded capacitors are used to improve linearity. The prototype achieves 104.3dB spurious-free dynamic range (SFDR) at 3.9kHz input signal while operating at sampling rate of 1 MS/s and the power consumption is 7.85 mW.