Investigation of logic circuit soft error rate (SER) in 14nm FinFET technology

Abstract

This paper presents characterization results of soft error rate (SER) on logic circuits manufactured with 14 nm High-k/metal gate bulk FinFET technology. The FinFET SER advantage seen on SRAM was also validated on logic circuits (5-10X improvement). Alpha irradiation results reveal that charge collection only on NMOS on low critical charge can contribute to SEU. Adding NMOS on low critical charge can increase error rate, yet it can be easily mitigated by the design change. Design schemes for low-power has little impact to the SER. Single event transient on clock-line in 14 nm FinFET was substantially improved from planer-MOS.