2-Gb/s/pin DDR3 memory channel design and simulation for carbon reduction

Abstract

The fabless semiconductor companies should take more responsibility for the global climate change when more and more consumer electronics are being produced. Under the trade-off between the signal quality of DDR3 memory and power consumption, the chip-package-board co-simulations were taken in the frequency domain up to 10 GHz and the time domain at 2 Gb/s to compare two types of channel designs. Results indicated that the proposed channel using the 2.5-layer PCB achieved the lower power consumption with acceptable eye diagrams of overlapping one DDR3 data byte that demonstrated 218-ps eye-aperture time, 1.47-V overshoot, and -0.05-V undershoot for the writing access, and 245-ps eye-aperture time, 1.83-V overshoot, and -0.25-V undershoot for the reading access. Moreover, there would be about 58 tons of carbon reduction per day if one third of global LCD TVs shipped each year use the 2.5-layer PCB design and the low-carbon DDR3 settings. Revising JEDEC Standard to implement two more weak drive strengths in the DDR3 SDRAM is recommended that is beneficial to reduce more power consumption in the consumer electronics.