Electromigration modeling with consideration of hillock formation

Abstract

This paper investigates the electromigration induced hillock generation in a wafer level interconnect structure through numerical approach. The electronic migration formulation that considers the effects of the electron wind force, stress gradients, temperature gradients, as well as the atomic density gradient has been developed. The parameter study for the Al line geometry with different width and thickness of a SWEAT structure is investigated. The comparison of void/hillock formation and the time to failure (TTF) life through numerical example of the SWEAT structure with the measurement result are studied and discussed. Finally, the TTF life of a hillock is defined and discussed.