Faster Localization of Logic Soft Failures Using a Combination of Scan Diagnosis at Reduced VDD and LADA

Abstract

In recent years, understanding the root cause of soft failures has been of considerable interest because it is challenging yet prevalent in advanced technologies. With increasing demands for faster diagnostic to issue fix, it is important to explore new methodologies that enable fast fault localization which is typically the bottleneck. Currently, laser-assisted device alteration (LADA) is well-established to reveal circuit speed paths or device limiters that respond to laser stimulation. It is effective but suffers from long inspection time which is worse on large chips. In this paper, a first localization step based on an unconventional application of scan diagnosis is proposed prior to LADA execution. This gives rise to a more precise search area, hence, a significant reduction in the turnaround time for laser interrogation. A case study illustrates.